1. Field of the Invention
The present invention relates in general to an improved multiprocessor data processing system and, in particular, to an improved method and system for input/output control in a multiprocessor system. Still more particularly, the present invention relates to a method and system for input/output control of simultaneous variable-width bus access by multiple processors in a multiprocessing system.
2. Description of the Prior Art
A multiprocessing system is a computing system which employs two or more connected processing units which execute programs simultaneously. The objective of such systems is increased speed or computing power by the carrying out of multiple processes simultaneously within a single system.
In such systems, a number of substantially equal processors are often coupled together over a common bus to a system memory or other I/O devices. Sharing of the bus or the provision of multiple bus units is required in order to use most efficiently multiple processor assets.
In such systems, it is desirable to access data over the system bus with a minimum delay. Large data transfers may require large bandwidth on the system bus while other processes may need only a small amount of data. For example, an instruction cache miss may require quick access to a large amount of data or instruction stalls may result. Alternatively, a "test and set" operation may only require a byte or two of data.
The fact that processors may need to access either large or small amounts of data and the disparity in bus sizes between processors and selected peripheral devices has led to some development in variable-width buses. For example, U.S. Pat. No. 5,300,811 discloses an integrated circuit device which can vary the effective bit width of a data bus by means of software instructions. Thus, a microprocessor is provided which may access the external data bus utilizing a width of 8 bits, 16 bits, 32 bits, etc., by dynamic bus sizing.
U.S. Pat. No. 5,408,628 discloses a solid-state data recorder which employs a solid-state memory to record data in the form of data words of variable length which may be transmitted from the memory on a flexible-width data bus. Bus lines are selected from among the total number of bus lines in accordance with the mapped-out memory locations in order to transfer the variable-length data words to and from the memory in order to minimize loss of usable recording space in the memory.
U.S. Pat. No. 5,515,507 discloses a multiple-width data bus for a microsequencer bus controller system so that data may be transferred either as full words or half words in order to permit the processor to communicate with subsystems which may have different word sizes.
U.S. Pat. No. 5,423,009 also discloses a dynamic-sizing bus controller which may be utilized with a host device having a host bus of a predetermined physical bus width and a slave device having a slave bus of a variable one of multiple possible logical bus widths. Finally, U.S. Pat. No. 5,394,528 discloses a data processor having bus-sizing function which permits data access to occur based upon the variable size of the data to be transferred.
While many of these systems disclose a technique whereby the width of a bus may be dynamically altered, none of these systems is directed to the concept of addressing the variable data access requirements of multiple processors in a multiprocessor system.
It thus should be apparent that a need exists for an input/output system whereby bus arbitration between multiple processors in a multiprocessor system may be utilized to effectively and efficiently access data within the system by utilizing all or a portion of a common wide bus.